ML505_RINGCNT Project Status | |||
Project File: | ml505_ringcnt.ise | Current State: | Programming File Generated |
Module Name: | ml505 |
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No Errors |
Target Device: | xc5vlx50t-3ff1136 |
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1 Warning |
Product Version: | ISE 9.2.02i |
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vie 5. oct 09:26:13 2007 |
ML505_RINGCNT Partition Summary | |||
No partition information was found. |
Device Utilization Summary | ||||
Slice Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Registers | 33 | 28,800 | 1% | |
Number used as Flip Flops | 33 | |||
Number of Slice LUTs | 7 | 28,800 | 1% | |
Number used as logic | 7 | 28,800 | 1% | |
Number using O6 output only | 7 | |||
Slice Logic Distribution | ||||
Number of occupied Slices | 9 | 7,200 | 1% | |
Number of LUT Flip Flop pairs used | 33 | |||
Number with an unused Flip Flop | 0 | 33 | 0% | |
Number with an unused LUT | 26 | 33 | 78% | |
Number of fully used LUT-FF pairs | 7 | 33 | 21% | |
Number of unique control sets | 1 | |||
IO Utilization | ||||
Number of bonded IOBs | 66 | 480 | 13% | |
Specific Feature Utilization | ||||
Number of BUFG/BUFGCTRLs | 1 | 32 | 3% | |
Number used as BUFGs | 1 | |||
Total equivalent gate count for design | 313 | |||
Additional JTAG gate count for IOBs | 3,168 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | jue 4. oct 19:07:02 2007 | 0 | 0 | 0 |
Translation Report | Current | jue 4. oct 19:07:20 2007 | 0 | 0 | 0 |
Map Report | Current | jue 4. oct 19:09:07 2007 | 0 | 1 Warning | 7 Infos |
Place and Route Report | Current | jue 4. oct 19:10:10 2007 | 0 | 0 | 3 Infos |
Static Timing Report | Current | jue 4. oct 19:11:03 2007 | 0 | 0 | 3 Infos |
Bitgen Report | Current | jue 4. oct 19:13:03 2007 | 0 | 0 | 0 |